I believe Mojo and Max represent the next generation of AI infrastructure. So, if more hardware companies want to leverage this software stack to support their unique accelerators, what key steps would they likely need to take?
We’re not quite ready to expand to arbitrary accelerators yet (we have quite a lot to get done in the next quarter or perhaps two). That said, you can prepare by building an high quality code generator for your chip, e.g. an LLVM backend. This should do register allocation and scheduling, and should expose the fancy features of your architecture with intrinsics or assembly instructions.
2 Likes