Mojo RISC-V Support

[owenhilyard]

Si-Five is starting to ship RISC-V boards that are powerful enough for use as embedded systems and to use in a lot of “raspberry pi workloads”, as well as having a respectable onboard NPU. Any thoughts on providing a tier 3 target? The reason I suggest tier 3 is because it doesn’t come with an expectation of being run in CI and is treated as a “nice to have” instead of build breaking when things go wrong. This should mean it’s simply cross compiling the runtime/compiler for RISC-V and adding a flag. We may also want to look at and adapt the way Rust does target tiers for Mojo. For example, splitting MAX off and having it support targets separately, or providing a gradual on-ramp for Windows support.